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NB4L7210 2.5V/3.3V Differential 2x10 Crosspoint Clock Driver with SDI Programmable Output Selects
The NB4L7210 is a Clock input crosspoint fanout distribution device selecting between one of two input clocks on each of the 10 differential output pairs. A 10 Bit Serial Data Interface programs each output MUX to asynchronously select either Input clock. CLOCK inputs can accept LVCMOS, LVTTL, LVPECL, CML, or LVDS signal levels and incorporate an internal 50 ohms on die termination resistors. SCLK, SDATA, and SLOAD input can accept single ended LVPECL, CML, LVCMOS, LVTTL signals levels. SCLK and SDATA inputs operate up to 20 MHz. SLOAD input loads and latches the output select data. The SDATAOUT pin permits cascading multiple devices. Outputs are optimized for minimal output-to-output skew and low jitter.
Features http://onsemi.com MARKING DIAGRAM*
52 1
1 52
QFN52 MN SUFFIX CASE 485M NB4L7210 A WL YY WW G
NB4L 7210 AWLYYWWG
* * * * * * * * * * *
Typical Input Clock Frequency > 2 GHz 200 ps Typical Rise and Fall Times 800 ps Typical Propagation Delay Output to Output Skew 150 ps Additive RMS Phase Jitter of 0.2 ps Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V Differential LVPECL Output Level (Typ 700 mV Peak-to-Peak) Low Profile 8x8 mm, 52 QFN Package 10GE WAN: 155.52 MHz / 622.08 MHz 10GE LAN: 161.1328 MHz These are Pb-Free Devices*
= Device Code = Assembly Site = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
Q0 Q0b VTCLK0 CLK0 CLK0b VTCLK0b Q1 Q1b
VTCLK1 CLK1 CLK1b VTCLK1b
Q8 Q8b
Q9 Q9b VCC VEE SCLK SDATA SLOAD
SDATAOUT
Figure 1. Functional Block Diagram ORDERING INFORMATION
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
August, 2009 - Rev. 7
1
Publication Order Number: NB4L7210/D
NB4L7210
SDATAOUT
VCC0
VCC1
VCC2
GND
VCC
Q0
Q0
Q1
Q1
GND
Q2
Q2
52 51 50 49 48 47 46 45 44 43 42 41 40 GND SLOAD VTCLK0 CLK0 CLK0 VTCLK0 GND VTCLK1 CLK1 CLK1 VTCLK1 SDATA GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SCLK Q7 VCC8 VCC9 VCC7 GND Q8 Q9 VCC Q9 Q8 Q7 GND NB4L7210
Exposed Pad (EP) 39 VCC3 38 Q3 37 Q3 36 VCC4 35 Q4 34 Q4 33 GND 32 Q5 31 Q5 30 VCC5 29 Q6 28 Q6 27 VCC6
Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION
Pin 1, 7, 13, 25, 26, 33, 40, 41 2 3, 6, 8, 11 Name GND SLOAD VTCLK0, VTCLK0, VTCLK1, VTCLK1 CLK0, CLK1 CLK0, CLK1 SDATA SCLK VCC, VCC9, VCC8, VCC7, VCC6, VCC5, VCC4, VCC3, VCC2, VCC1, VCC0 Q[9-0] Q[9-0] SDATAOUT EP I/O Supply LVCMOS, LVTTL Termination- Description Negative Supply pins must be all externally connected to a power supply to guarantee proper operation. Serial Load and Latch control input pin. Defaults LOW when floating open. Internal 50 Ohms Termination Resistor connection Pins. In the differential configuration when the input termination pins are connected to the common termination voltage. CLOCK Input (TRUE). If no signal is applied then the device may be susceptible to self oscillation. CLOCK Input (INVERT). If no signal is applied then the device may be susceptible to self oscillation. Serial Data input pin (for BITS 0:9, a "0" selects CLK1, "1" selects CLK 0). Defaults LOW when floating open. Serial Load Clock input pin. Defaults LOW when floating open. Positive Supply pins must be all externally connected to a power supply to guarantee proper operation.
4, 9 5, 10 12 14 15, 16, 19, 22, 27, 30, 36, 39, 44, 47, 50, 51 17, 20, 23, 28, 31, 34, 37, 42, 45, 48 18, 21, 24, 29, 32, 35, 38, 43, 46, 49 52 Exposed Pad
Differential LVPECL, CML, or LVDS Differential LVPECL, CML, or LVDS LVCMOS, LVTTL LVCMOS, LVTTL Supply
LVPECL LVPECL LVCMOS, LVTTL GND
Output (INVERT) Output (TRUE) Serial Data output pin for cascade Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat- sinking conduit for proper thermal operation and must be connected to GND.
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10 MUXes Output Qx BIT SDATAOUT 9876543210 9876543210 MSB LSB
SLOAD SDATA SCLK
10 Bit LATCH 10 Bit SHIFT
SDATA REGISTER DATA BIT VALUE 0 Selects CLK1 / CLK1 1 Selects CLK0 / CLK0 (C)
SDATA 10 BIT REGISTER 10 Bit SHIFT REGISTER (A) (B)
Figure 3. Serial Data Interface Table 2. ATTRIBUTES
Characteristic Input Default State Resistors ESD Protection Human Body Model QFN-52 Value None > 2 kV Level 1 UL 94 V-0 @ 0.125 in 2027
Moisture Sensitivity Pb-Free Package (Note 1) Flammability Rating Transistor Count
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol VCC VI IIN VINPP IOUT TA Tstg qJA qJC Tsol Positive Power Supply Positive Input Input Current Through RT (50 W Resistor) Differential Input Voltage Output Current (Q / Q) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 2) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 lfpm 500 lfpm 2S2P (Note 2) QFN-52 QFN-52 QFN-52 Continuous Surge QFN-52 Parameter Condition 1 GND = 0 V GND = 0 V Static Surge Condition 2 Rating 6.0 GND-0.3 VI VCC 35 70 2.5 25 50 -40 to +85 -65 to +150 25 19.6 21 265 Unit V V mA mA V mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). 3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 4. DC CHARACTERISTICS (VCC = 2.375 V to 3.6 V, VEE = 0 V, TA = -40C to +85C (Note 4))
Symbol IEED RTIN VOH VOL IIH IIL Vth VIH VIL VINAMP VCMR VIHD VILD VID VIH VIL VOH VOL Characteristic GND Supply Current (All Outputs Loaded) Internal Input Termination Resistor Output HIGH Voltage Output LOW Voltage Input HIGH Current (VTx/VTx open) Input LOW Current (VTx/VTx open) 150 Min 110 40 VCC-1145 VCC-1945 Typ 150 50 VCC-1020 VCC-1820 8 0.1 Max 200 60 VCC-895 VCC-1695 150 Unit mA W mV mV mA mA
DIFFERENTIAL INPUTS DRIVEN SINGLE-ENDED (Figures 5, 6) Input Threshold Reference Voltage Range (Note 5) Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage Single-Ended Input Amplitude GND +950 Vth + 150 GND 300 VCC - 150 VCC Vth - 150 VCC VCC - 75 VCC VCMR - 75 2400 mV mV mV mV mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8) Input Common Mode Range Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD - VILD) Input HIGH Voltage Input LOW Voltage GND +950 VCMR + 75 GND 150
LVCMOS/LVTTL INPUTS (SCLK, SDATA, SLOAD) 2.0 GND VCC 0.8 V V
LVCMOS/LVTTL OUTPUTS (SDATAOUT) Output HIGH Voltage @ IOH = -1.0 mA, RL = 20 kW to GND Output LOW Voltage @ IOL = 1.0 mA, RL = 20 kW to GND 2.0 3.2 0.25 0.5 V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and Output parameters vary 1:1 with VCC. Outputs loaded with 50 W to VCC - 2.0 V (See Figure 16) except SDATAOUT. 5. Vth is applied to the complementary input when operating in single-ended mode.
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Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.6 V, GND = 0 V, TA = -40C to +85C (Note 6))
Symbol VOUTPP tPLH, tPHL tSKEW Characteristic Output Voltage Amplitude @ VINPPmin (See Figure 9) Propagation Delay to (See Figure 9) fin = 100 MHz fin = 1 GHz Min 650 530 610 6.5 -5 0 0 SDATA to SCLK Measured at 1.5 V SCLK to SLOAD+ Measured at 1.5 V SDATA to SCLK SLOAD @155.52 MHz @ 622.08 MHz -150 1000 325 2.0 See Fig 10 See Fig 11 1.7 0.63 3.9 150 750 1200 Typ 800 790 725 20 2 5 20 -115 345 365 Max 875 960 875 30.8 10 35 200 Unit mV
CLK/CLK to Qx/Qx (Note 7) SCLK to SDATAOUT Measured at 1.5 V
ps ns ps
Duty Cycle Skew (Note 8) Within -Device Skew Device to Device Skew (Note 8) Setup Time
ts
ps
Th PWmin tJIT(O)
Hold Time Minimum Pulse Width
ps ns fs
RMS Phase Jitter, Integration Range 12 KHz to 20 MHz
tJITTER
TIE Rj (10,000 Cycles)
@155.52 MHz @ 622.08 MHz Crosstalk RMS Jitter RMS (1000 Cycles) (Note 9)
ps
VINPP tr , tf
Input Voltage Swing/Sensitivity (Differential Configuration, measured Single-ended on each input) Output Risetime and Falltime Qx/Qx (20% to 80%) SDATAOUT (0.8 V - 2.0 V)
mV
120 0.88
185 10
260 15
ps ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Measured by forcing VINPP (Typ 750 mVPP) from a 50% duty cycle clock source. Q/Q Outputs loaded with 50 W to VCC - 2.0 V (See Figure 16). SCLK, SDATA and SLOAD at LOW SDATAOUT loaded 20 kW and 15 pF to GND. 7. Measured from the input pair crosspoint to each single output pair crosspoint. 8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+. 9. 155.52 MHz @ 750 mVPP input on measured output, 161.13 MHz @ 850 mVPP input on all other others.
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Programming Application Information for the SDI
To use the serial port, the SCLK signal samples the information on the SDATA line and indexes the data into a 10 bit shift register (See Figure 3). The register shifts once per rising edge of the SCLK input. The serial input SDATA bits must each meet setup and hold timing to their respective SCLK rising edge as specified in the AC Characteristics section of this document. (See Figure 4) The SDATA Least Significant Bit (LSB), D0, is indexed in first and the Most Least Significant Bit (LSB), D9, is indexed in last. A Pulse on the SLOAD pin after the SHIFT register is fully indexed (10 clocks) will load and lock the MUX select data values into the Latch register (See Figure 4). For each MUX (Output Q[0:9], a "0" bit value selects CLK1 and a "1" bit value selects CLK 0 (see Figure 3, "C").
As shown in Figure 4, the SLOAD pulse Low to HIGH level transition transfers the data from the SHIFT register to the LATCH register. The SLOAD Pulse HIGH to LOW level transition will lock the new MUX select data values into the LATCH register. An initial program load cycle is recommended since the 10 bit register will power-up in a random state. SDATAOUT pin outputs the shift register LSB bit with each SCLK rising edge for porting to the SCLK of the next device in a cascade interconnect only. Cascade operation will require a complete data register loading of all devices to purge the shift registers of power up random state bits.
SDATA to SCLOCK ts th C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
SCLK
SDATA
D0 LSB
D1
D2
D3
D4
D5
D6
D7
D8
D9 MSB
SLOAD SDATA to SLOAD ts PWmin
Figure 4. Serial Interface Timing Diagram
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NB4L7210
VIH Vth VIL CLK Qx CLK Qx
Vth
Figure 5. Differential Input Driven Single-Ended Vth Schema
VCC Vthmax CLKx Vth Vthmin GND
VIHmax VILmax
VIHmin CLKx VILmin
Figure 6. Differential Input Driven Single-Ended Vth Diagram
CLK
Q
CLK
Q
Figure 7. Differential Inputs Driven Differentially
VCC
VIH(MAX) VIL VIH VINPP = VIHD - VILD VIL VIH
VCMR
GND
VIL(MIN)
Figure 8. VCMR Diagram
CLK CLK Q
VINPP = VIH - VIL
VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 9. AC Reference Measurement http://onsemi.com
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NB4L7210
Figure 10. With conditions of an Input (source) noise floor below the NB4L7210 device noise floor, additive Phase Noise with a 155.52 MHz Carrier (Agilent 8665A) is revealed. Note near zero additive Phase Noise below 100 kHz offset. From 100 kHz to 20 MHz additive (residual) integrated phase noise Jitter is about 200 fs RMS.
Figure 11. With conditions of an Input (source) noise floor below the NB4L7210 device noise floor, additive Phase Noise with a 622.08 MHz Carrier (Agilent 8665A) is revealed. Note near zero additive Phase Noise below 50 kHz offset. From 50 kHz to 20 MHz additive (residual) integrated phase noise Jitter is about 200 fs RMS. http://onsemi.com
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VCC VCC
Z = 50 W LVTTL/ LVCMOS Driver No Connect No Connect VREF
CLK VTCLK 50 W NB4L7210 VTCLK CLK 60 pF VCC 50 W Recommended VREF Values VREF LVCMOS VCC - VEE 2 LVTTL 1.5 V
VEE
Figure 12. LVCMOS/LVTTL to NB4L7210 Receiver Interface
VCC VCC
Z = 50 W LVPECL Driver Recommended RT Values VCC 2.5 V RT RT VEE VEE RT 50 W Z = 50 W 3.3 V 120 W
CLK VTCLK VTCLK CLK 50 W NB4L7210 50 W
VEE
Figure 13. LVPECL to NB4L7210 Receiver Interface
VCC VCC
50 W
50 W
Q
Z = 50 W VCC VCC
CLK VTCLK VTCLK CLK VEE 50 W 50 W NB4L7210
CML Driver
Q VEE
Z = 50 W
Figure 14. CML to NB4L7210 Interface
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VCC VCC
Z = 50 W LVDS Driver Z = 50 W
CLK VTCLK VTCLK CLK 50 W NB4L7210 50 W
VEE
VEE
Figure 15. LVDS to NB4L7210 Receiver Interface
Q NB4L7210 Q
Zo = 50 W
D Receiver
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 16. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device NB4L7210MNG NB4L7210MNTXG Package QFN-52 (Pb-Free) QFN-52 (Pb-Free) Shipping 46 Units / Rail 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB4L7210
PACKAGE DIMENSIONS
52 PIN QFN 8x8 CASE 485M-01 ISSUE B
D A B
PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 --0.30 0.50
2X
0.15
2X
C 0.15 C A2
0.10 C A 0.08 C
SEATING PLANE
A1 D2
14
52 X
L
13
1 52 X
K
The products described herein (NB4L7210), may be covered by U.S. patents including 6,362,644. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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EEEE EEEE EEEE EEEE
A3
REF 26 27
E
DIM A A1 A2 A3 b D D2 E E2 e K L
C
E2
39 52 40
e
52 X
b
NOTE 3
0.10 C A B 0.05 C
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NB4L7210/D

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